| 发明名称 |
FAIL-SAFE I/O TO ACHIEVE ULTRA LOW SYSTEM POWER |
| 摘要 |
The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold. |
| 申请公布号 |
US2016035412(A1) |
申请公布日期 |
2016.02.04 |
| 申请号 |
US201514813949 |
申请日期 |
2015.07.30 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
VYAVAHARE Prajkta;CHAUHAN Rajat;KOTHAMASU Siva Srinivas |
| 分类号 |
G11C11/4093;H03K17/687;G06F13/10;G11C11/4074 |
主分类号 |
G11C11/4093 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An input/output (IO) circuit powered by an input/output (IO) supply voltage, the IO circuit comprising:
a cutoff circuit configured to receive a first invert signal, the IO supply voltage, a bias voltage and a pad voltage; an output stage coupled to the cutoff circuit, and configured to receive a first signal, a second signal and the bias voltage; and a pad coupled to the output stage, and a voltage generated at the pad is the pad voltage, wherein the cutoff circuit and the output stage are configured to maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold. |
| 地址 |
Dallas TX US |
