| 摘要 |
This invention comprises a symmetrical port-to-port circuit which has a first port comprising first and second terminals and a second port comprising third and fourth terminals, and in which odd-numbered stage circuits and an even-numbered stage circuit are connected in a three-stage cascade. The odd-numbered stage circuits comprise one of a stage in which an impedance element is disposed on a series arm only and a stage in which the impedance element is disposed on a shunt only, while the even-numbered stage circuit comprises the other of the stage in which the impedance element is disposed on a series arm only and the stage in which the impedance element is disposed on a shunt only. The absolute values of the stage impedance values of the odd-numbered stage circuits are set to be equal to the absolute value of the stage impedance value of the even-numbered stage circuit, while the signs of the stage impedance values of the odd-numbered stage circuits are set to be different from the sign of the stage impedance value of the even-numbered stage circuit. |
