HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS ENHANCEMENT PLUG AND METHOD

摘要

A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to its neighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral mis-registration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric region atop the MOSFET array forms self-guided source and body contacts through the SGCEP.

主权项

1. A method for fabricating a high density trench-gated MOSFET array device, expressed in an X-Y-Z coordinate system with an X-Y plane parallel a major semiconductor chip plane, comprising:
providing a semiconductor substrate; providing an epitaxial region overlying the substrate; forming an array of active trenches comprising a plurality of trench gate stacks in a MOSFET array area, each trench gate stack having a poly-silicon gate embedded in a gate oxide shell and a gate oxidation on top, having predetermined separations along the X-Y plane; implanting a body implant region embedded into a top portion of the epitaxial region in the MOSFET array area, and implanting a source implant region embedded into the top portion of the epitaxial region and atop the body implant region in the MOSFET array area; forming a plurality of silicon nitride spacer caps, each silicon nitride spacer cap being laterally registered, in the X-Y plane, to the gate oxide shell of a trench gate stack such that in the Z direction, a center line of each silicon nitride spacer cap substantially overlaps with a center line of each gate oxide shell to which the silicon nitride spacer cap corresponds, each trench gate stack and corresponding silicon nitride spacer cap in the MOSFET array area constitute an active nitride-capped trench gate stacks (ANCTGS); depositing a dielectric region atop the MOSFET array structure; forming a contact opening between each pair of adjacent ANCTGS through the dielectric region, the contact opening penetrates into the source implant region and the body implant region; forming a self-guided contact enhancement (“SGCEP”) in each contact opening, each SGCEP comprises:
a lower intimate contact enhancement section (ICES) in accurate registration, along the X-Y plane, to adjacent ANCTGS; andan upper distal contact enhancement section (DCES) above the ICES, said DCES having a lateral (along the X-Y plane) mis-registration (LTMSRG) to said neighboring ANCTGS;an intervening tapered transitional section (TTS) located between and bridging the ICES and the DCES.