发明名称 |
Work function adjustment by carbon implant in semiconductor devices including gate structure |
摘要 |
A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed. |
申请公布号 |
US9252146(B2) |
申请公布日期 |
2016.02.02 |
申请号 |
US201414280751 |
申请日期 |
2014.05.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Liang Yue;Guo Dechao;Henson William K.;Narasimha Shreesh;Wang Yanfeng |
分类号 |
H01L21/70;H01L27/12;H01L21/00;H01L21/425;H01L27/092;H01L21/8238;H01L21/265;H01L21/28;H01L29/10;H01L29/51 |
主分类号 |
H01L21/70 |
代理机构 |
Scully, Scott, Murphy & Presser, P.C. |
代理人 |
Scully, Scott, Murphy & Presser, P.C. ;Meyers, Esq. Steven J. |
主权项 |
1. A semiconductor device comprising:
a semiconductor substrate comprising a first device region and a second device region; a p-type semiconductor device in the first device region comprising a first gate structure and a first source region and a first drain region on opposing sides of the first gate structure having a p-type conductivity, wherein the first gate structure comprises a first gate conductor layer overlying a first high-k gate dielectric layer; and an n-type semiconductor device in the second device region comprising a second gate structure and a second source region and a second drain region on opposing sides of the second gate structure having an n-type conductivity, wherein the second gate structure comprises a second gate conductor layer overlying a second high-k gate dielectric layer and a spacer in direct physical contact with outer sidewalls of said second gate conductor layer and said second high-k gate dielectric layer, wherein a bottommost surface of said spacer is in direct physical contact with a topmost surface of a carbon dopant, wherein said carbon dopant is present at an interface between the second high-k gate dielectric layer, the spacer and the semiconductor substrate, and wherein said carbon dopant is present across an entirety of a topmost surface of said semiconductor substrate in the second device region. |
地址 |
Armonk NY US |