发明名称 Semiconductor device having multilayer wiring structure and manufacturing method of the same
摘要 Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.
申请公布号 US9252099(B2) 申请公布日期 2016.02.02
申请号 US201113235782 申请日期 2011.09.19
申请人 TERA PROBE, INC. 发明人 Arai Kazuyoshi
分类号 H01L23/48;H01L23/522;H01L23/31;H01L25/065;H01L25/00;H01L25/16;H01L23/00 主分类号 H01L23/48
代理机构 Holtz, Holtz & Volek PC 代理人 Holtz, Holtz & Volek PC
主权项 1. A semiconductor device comprising: a semiconductor chip comprising: a semiconductor substrate;an integrated circuit, a plurality of terminals, and a passivation film provided on an upper surface of the semiconductor substrate; anda resin sealing layer formed on the passivation film so as to coat the upper surface of the semiconductor substrate; a multilayer wiring structure stacked on the semiconductor chip; and an electronic component embedded in the multilayer wiring structure; wherein the multilayer wiring structure has a plurality of insulating layers and a plurality of layers of wiring patterns which are stacked on each other in an alternating manner on the semiconductor chip inside an outer edge of the semiconductor chip as viewed from above; wherein the multilayer wiring structure further includes an interlayer connection conductor which is provided in an insulating layer from among the plurality of insulating layers so as to penetrate the insulating layer; wherein all of the plurality of layers of wiring patterns, the interlayer connection conductor, and the electronic component are located inside the outer edge of the semiconductor chip as viewed from above; and wherein the plurality of insulating layers include an insulating layer formed by curing prepreg.
地址 Yokohama, Kanagawa JP