III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS

摘要

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

主权项

1. A semiconductor device, comprising:
a substrate having a plurality of fins extending therefrom, including first and second fins, each fin including a channel region; a gate electrode over each channel region, wherein a gate dielectric layer is provided between each gate electrode and the corresponding channel region; p-type source/drain regions in or on the firs fin and adjacent to the corresponding channel region and comprising semiconductor material; n-type source/drain regions in or on the second fin and adjacent to the corresponding channel region and comprising semiconductor material; a III-V semiconductor material layer on at least a portion of the p-type source/drain regions and a portion of the n-type source/drain regions; and at least one metal contact on the III-V semiconductor material layer.