| 主权项 |
1. An information processing device comprising:
a plurality of processors including an Acquire side processor intending to read data and a Release side processor intending to write data; and a shared memory, the Acquire side processor and the Release side processor including a cache, a memory access control unit configured to control access from the processors to the shared memory, the memory access control unit in the Release side processor, configured to comprise a store counter whose value is increased if a Store instruction is issued to the shared memory, and is decreased if an acknowledgement response indicating correct reception of the Store instruction is received from the shared memory, and a wait counter whose value is set at a value representing a predetermined time if the store counter has come to indicate 0, the wait counter decreasing the value at every predetermined interval, and the predetermined time being determined such that, compared to a time since the shared memory's sending the invalidation request until the Acquire side processor's completing the process for invalidating the cache, longer is a time taken totally by the shared memory's sending the acknowledgement response in response to the Store instruction from the Release side processor, the Release side processor's writing a flag into the shared memory the predetermined time later, and the Acquire side processor's reading the flag, and an invalidation request control unit configured to perform a process for invalidating the cache in accordance with the invalidation request from the shared memory, wherein, the shared memory sends an invalidation request to the Acquire side processor for invalidating a cash in the Acquire side processor, based on writing of data by the Release side processor, the memory access control unit in the Release side processor issues the StoreFence instruction if both of the store counter and the wait counter have come to indicate 0, and the memory access control unit in the Acquire side processor issues a LoadFence instruction in response to the StoreFence instruction for guaranteeing completion of the cache invalidation in accordance with the invalidation request from the shared memory after completing a process for the cache invalidation. |
