| 主权项 |
1. A method comprising:
within a processor: determining an initial delay across each clock to out path in a bus including a plurality of clock to out paths for a programmable logic device; for each pair of clock to out paths in the bus, determining a delay difference between the initial delay across a first clock to out path in the pair and the initial delay across a remaining second clock to out path in the pair, wherein the initial delay for each clock to out path is constrained by a maximum delay between the initial delay and a corresponding clock out delay as well as a minimum delay between the initial delay and the corresponding clock out delay; for each pair of clock to out paths, determining a first difference between the minimum delay for the first clock to out path and the maximum delay for the second clock to out path and determining a second difference between the maximum delay for the first clock to out path and the minimum delay for the second clock to out path; and determining an individual delay offset range to be added to the initial delay for each of the clock to out paths using the delay differences, the first differences, and the second differences. |
