发明名称 Resistance-change semiconductor memory
摘要 According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared.
申请公布号 US9245607(B2) 申请公布日期 2016.01.26
申请号 US201313763303 申请日期 2013.02.08
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Inaba Tsuneo
分类号 G11C11/00;G11C11/16;G11C5/06;G11C11/02;G11C5/08 主分类号 G11C11/00
代理机构 Knobbe, Martens, Olson & Bear, LLP 代理人 Knobbe, Martens, Olson & Bear, LLP
主权项 1. A resistance change type semiconductor memory comprising: active areas which extend to a first direction isolation areas which extend to the first direction and are adjacent to the active areas in a second direction crossing the first direction; first and second memory cells provided in one of the active areas and aligned in the first direction; and isolation transistor electrically separating the first and second memory cells, wherein each of the first and second memory cells comprises a magnetoresistive element and a cell transistor connected to the magnetoresistive element in series, and the active areas and the isolation areas arranged as a line-and-space pattern.
地址 JP