Clock synchronization circuit and semiconductor memory device including clock synchronization circuit

摘要

A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.

主权项

1. A clock synchronization circuit comprising:
a delay-locked loop (DLL) configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal; and a delay-locked control unit configured to detect the locked state of the DLL, and to generate a delay-locked disable signal when the locked state is detected as being maintained for a predetermined period of time, wherein the DLL is responsive to the delay-locked disable signal to terminate the delay-locking operation in which the delay time is adjusted, wherein the delay-locked control unit is configured to generate the delay-locked disable signal responsive to an obtained court value of the input clock signal, wherein the delay-locked control unit comprises:
a locked detector that determines whether the DLL is in the locked state, and outputs a delay-locked signal; anda counter that counts a time in which the locked state is maintained based on the delay-locked signal to obtain the count value, and to output the delay-locked disable signal when the count value is equal to or greater than a predetermined value, and wherein the counter counts the input clock signal when the delay-locked signal has first logic level, and the counter is rest when the delay-locked signal has a second logic level.