DESIGN SIMULATION USING PARALLEL PROCESSORS

摘要

A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

主权项

1. A method for design simulation, comprising:
partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE; providing a multiprocessor device, which comprises a second plurality of processors operating in parallel, and when provided a sequence of PEs, it distributes the PEs to processors in the order of the PEs in the sequence, according to a built in scheduling policy; computing an order for executing the PEs, such that when a sequence of PEs in the computed order is provided to the multiprocessor device, the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device; providing the computed sequence of PEs to the multiprocessor device for execution; executing the PEs on the processors, by the multiprocessor device, in accordance with the computed order and the scheduling policy, to produce a simulation result; and verifying a performance of the design responsively to the simulation result.