| 发明名称 |
RECESS TECHNIQUE TO EMBED FLASH MEMORY IN SOI TECHNOLOGY |
| 摘要 |
Some embodiments of the present disclosure provide an integrated circuit arranged on a silicon-on-insulator (SOI) substrate region. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer. |
| 申请公布号 |
US2016020219(A1) |
申请公布日期 |
2016.01.21 |
| 申请号 |
US201414332556 |
申请日期 |
2014.07.16 |
| 申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Chuang Harry-Hak-Lay;Wu Wei Cheng;You Kai-Shyang |
| 分类号 |
H01L27/115;H01L29/423;H01L21/265;H01L29/06;H01L29/49;H01L21/28;H01L27/12;H01L29/51 |
主分类号 |
H01L27/115 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit (IC) comprising:
a silicon-on-insulator (SOI) substrate region made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer; a recess extending downward from an upper surface of the silicon layer and terminating in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer; a first semiconductor device disposed on the recessed handle wafer surface; and a second semiconductor device disposed on the upper surface of the silicon layer. |
| 地址 |
Hsin-Chu TW |
