发明名称 COMBINED POWER AND INPUT/OUTPUT LINE
摘要 <p>An electronic device including a host system including a source; and a target system operably coupled to the host system via a combined power I/O line; wherein the target system includes a pass transistor and a switching system cooperative to allow the source to charge a power supply capacitor on the target system via the combined power I/O line in a first mode and alternately charge and discharge the power supply capacitor during a communication via the combined power I/O line in a second mode, wherein the alternately charging and discharging is in synchronization with said communication.</p>
申请公布号 EP2972923(A1) 申请公布日期 2016.01.20
申请号 EP20140712428 申请日期 2014.02.28
申请人 MICROCHIP TECHNOLOGY INCORPORATED 发明人 JULICHER, JOSEPH;SCHIEKE, PIETER;DELPORT, VIVIEN
分类号 G06F13/42;G05B19/042;G06F1/26;G06F13/40;H02J7/00;H04B3/54;H04L12/10;H04L12/40 主分类号 G06F13/42
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