| 主权项 |
1. A liquid crystal display comprising:
a liquid crystal display panel having data lines and gate lines crossing each other and a matrix of liquid crystal cells arranged by the crossing structure of the lines, the liquid crystal display panel being divided into at least four portions including a first portion, a second portion, a third portion and a fourth portion, wherein the first and third portions are disposed in a left portion of the liquid crystal display panel and the second and fourth portions are disposed in a right portion of the liquid crystal display panel; a first gate drive circuit that sequentially supplies a gate pulse to the gate lines present in the first portion and the second portion on the screen of the liquid crystal display panel in response to a gate output enable signal, wherein the second portion is apart from the first portion in a horizontal direction; a second gate drive circuit that sequentially supplies the gate pulse to the gate lines present in the third portion and the fourth portion on the screen of the liquid crystal display panel in response to the gate output enable signal, wherein the third portion is apart from the first portion in a vertical direction, and the fourth portion is apart from the third portion in the horizontal direction; a first data drive circuit that supplies a data voltage to the data lines present in the first portion and the third portion on the screen of the liquid crystal display panel in response to a first source output enable signal; a second data drive circuit that supplies the data voltage to the data lines present in the second portion and the fourth portion below the second portion on the screen of the liquid crystal display panel in response to a second source output enable signal; and a timing controller that generates the gate output enable signal, the first source output enable signal, and the second source output enable signal to control the gate pulse output timing of the gate drive circuits and the data voltage output timing and charge sharing timing of the data drive circuits, wherein the first source output enable signal controls the data voltage output timing and charge sharing timing of the first data drive circuit, and the second source output enable signal controls the data voltage output timing and charge sharing timing of the second data drive circuit in a different way from the first data drive circuit, wherein at least some of data output channels of the first data drive circuit for the data lines in the first and third portions are connected during the charge sharing timing of the first data drive circuit and are disconnected to supply the data voltage to the data lines in the first and third portions during the data voltage output timing of the first data drive circuit, and wherein at least some of data output channels of the second data drive circuit for the data lines in the second and fourth portions are connected during the charge sharing timing of the second data drive circuit and are disconnected to supply the data voltage to the data lines in the second and fourth portions during the data voltage output timing of the second data drive circuit. |
