Systems and Methods for Safely Subscribing to Locks Using Hardware Extensions

摘要

Transactional Lock Elision allows hardware transactions to execute unmodified critical sections protected by the same lock concurrently, by subscribing to the lock and verifying that it is available before committing the transaction. A “lazy subscription” optimization, which delays lock subscription, can potentially cause behavior that cannot occur when the critical sections are executed under the lock. Hardware extensions may provide mechanisms to ensure that lazy subscriptions are safe (e.g., that they result in correct behavior). Prior to executing a critical section transactionally, its lock and subscription code may be identified (e.g., by writing their locations to special registers). Prior to committing the transaction, the thread executing the critical section may verify that the correct lock was correctly subscribed to. If not, or if locations identified by the special registers have been modified, the transaction may be aborted. Nested critical sections associated with different lock types may invoke different subscription code.

主权项

1. A system, comprising:
one or more processor cores; a hardware transactional memory; and a memory coupled to the one or more processor cores and storing program instructions that when executed on the one or more processor cores cause the one or more processor cores to execute a multithreaded application that comprises a critical section, wherein the critical section is associated with a lock; wherein to execute the multithreaded application, the one or more processor cores are configured to:
begin execution of the multithreaded application;store, in a designated location prior to executing the critical section by a thread of one of the one or more processor cores, information identifying the lock that is associated with the critical section, wherein the information identifies the location at which the lock associated with the critical section resides in the hardware transactional memory; andbegin execution, by the thread, of the critical section using a hardware transaction; and wherein the one of the one or more processor cores is configured to abort the hardware transaction in response to determining that one or more of the stored information or the contents of the identified location has been modified during execution of the hardware transaction.