MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

摘要

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

主权项

1. A memory controller comprising:
request logic to generate a memory access request, the memory access request including command information and control information, the control information to be used by a memory device to receive the command information; a first output driver circuit to launch the control information to the memory device; and a second output driver circuit to launch the command information in accordance with a programmable offset, after launch of the control information.