DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE

摘要

A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.

主权项

1. A delay circuit comprising:
an input line to which an analog input signal is input; a plurality of analog signal memory devices; an output line from which an analog output signal is output; a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices; a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; and a clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches from a reference clock, the delay circuit delaying signals by controlling the plurality of sampling switches to accumulate the analog input signal in the plurality of analog signal memory devices and controlling the plurality of output switches to output the signals accumulated in the plurality of analog signal memory devices to the output line, wherein phase of the plurality of sampling switch control signals may be shifted with respect to phase of the plurality of output switch control signals.