| 摘要 |
The present invention provides a semiconductor device having a novel configuration. In a semiconductor device performing a pipeline process, a first arithmetic unit and a second arithmetic unit are provided to an execution stage, and a transistor for performing power gating is connected to the first arithmetic unit and the second arithmetic unit individually. In addition, the semiconductor device can perform fine grained power gating by providing power supply only to the arithmetic unit performing arithmetic, so that the power consumption of the semiconductor device can be reduced. A transistor for performing power gating includes an oxide semiconductor in a channel formation region, and a leakage current between power lines can be reduced. In addition, the transistor for performing power gating can be provided to a different layer from transistors in the arithmetic units, thereby reducing area overhead caused by the increase in the transistors. |
