CONTEXT SWITCHING MECHANISM FOR A PROCESSING CORE HAVING A GENERAL PURPOSE CPU CORE AND A TIGHTLY COUPLED ACCELERATOR

摘要

An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.