Techniques and configuration for stacking transistors of an integrated circuit device

摘要

Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

主权项

1. An apparatus comprising:
a semiconductor substrate; a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes:
a first isolation layer disposed on the semiconductor substrate,a first channel layer disposed on the first isolation layer,a second isolation layer disposed on the first channel layer, anda second channel layer disposed on the second isolation layer, wherein the first and second channel layers define a two-channel region of the fin structure that corresponds to a first portion of the first channel layer over which the second channel layer is disposed above the first channel layer, and a one-channel region of the fin structure that corresponds to a second portion of the first channel layer over which the second channel layer is not disposed above the first channel layer,
a first contact electrically coupled with the first channel layer in the one-channel region, the first contact and the first channel layer included in a first transistor, anda second contact electrically coupled with the second channel layer in the two-channel region, the second contact and the second channel layer included in a second transistor; and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for the first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for the second transistor.