发明名称 Dummy bit line MOS capacitor and device using the same
摘要 A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
申请公布号 US9236501(B2) 申请公布日期 2016.01.12
申请号 US201213692910 申请日期 2012.12.03
申请人 SK HYNIX INC. 发明人 Lim Jeong Sub
分类号 H01L27/108;H01L29/94;H01L29/66;H01L27/02;G11C7/18;H01L21/768 主分类号 H01L27/108
代理机构 代理人
主权项 1. A metal oxide semiconductor (MOS) capacitor, comprising: a gate buried in a semiconductor substrate; a first dielectric layer disposed between the gate and the semiconductor substrate; a first contact coupled to the semiconductor substrate at a first side of the gate; a second dielectric layer disposed on the semiconductor substrate at a second side of the gate; and a second contact disposed on the second dielectric layer and coupled to a dummy bit line in an outermost cell block of a cell array, wherein the second dielectric layer prevents direct electrical conduction between the second contact and the semiconductor substrate, and wherein the second contact is electrically insulated from the gate.
地址 Icheon KR