主权项 |
1. An integrated circuit comprising:
A. a TDI/TMS input lead; B. a TCK input lead; C. a TDO output lead; D. double data rate circuitry having an input coupled to the TDI/TMS input lead, an input coupled to the TCK input lead, and separate TDI and TMS output leads; E. addressable TAP interface circuitry having:
i. a TDI input coupled to the TDI output lead;ii. a TMS input coupled to the TMS output lead;iii. a TCK input coupled to the TCK input lead;iv. a TDO output coupled to the TDO output lead;v. a TDI output coupled to the TDI input;vi. a TMS output coupled to the TMS input;vii. a TCK output coupled to the TCK input;viii. a TDO input coupled to the TDO output; andix. shadow protocol circuitry including detection logic with inputs coupled to the TDI input, the TMS input, and the TDK input, an enable output; an address output, an address control output, and a match input, and including address circuitry having an address input coupled to the address output, an address control input coupled to the address control output, and a match output coupled to the match input; and F. a TAP domain having:
i. a TDI input coupled to the TDI output of the addressable TAP interface circuitry;ii. a TMS input coupled to the TMS output of the addressable TAP interface circuitry;iii. a TCK input coupled to the TCK output of the addressable TAP interface circuitry;iv. a TDO output coupled to the TDO input of the addressable TAP interface circuitry. |