CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

摘要

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

主权项

1. A system, comprising:
a host processor operable to generate Input/Output (I/O) requests; a host memory communicatively coupled to the host processor and sectioned into pages; a host bus adapter (HBA) communicatively coupled to the host processor to process the I/O requests, wherein the HBA comprises a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD); and an HBA driver operable on the host processor wherein the DRAM is sectioned into pages mapped to pages of the host memory, and the SSD is sectioned into pages mapped to pages of the DRAM, and wherein the HBA driver is operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.