发明名称 STRUCTURE AND METHOD OF BATCH-PACKAGING LOW PIN COUNT EMBEDDED SEMICONDUCTOR CHIPS
摘要 In a method of fabricating packaged semiconductor devices in panel format, a flat panel sheet as a carrier (100) is dimensioned for a set of contiguous chips and includes a stiff substrate (101) of an insulating plate, and a tape (102) having a surface layer (110) of a first adhesive releasable at elevated temperatures, a core base film (111), and a bottom layer (112) with a second adhesive attached to the substrate (101). The method includes attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Also, the method includes laminating a compliant insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set, grinding lamination material to expose the bumps, plasma-cleaning, and sputtering at least one layer of metal.
申请公布号 WO2016004238(A1) 申请公布日期 2016.01.07
申请号 WO2015US38880 申请日期 2015.07.01
申请人 TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS JAPAN LIMITED 发明人 MASUMOTO, MUTSUMI
分类号 H01L23/538;H01L21/56 主分类号 H01L23/538
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