发明名称 シフトレジスタの作製方法
摘要 The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.
申请公布号 JP5839747(B2) 申请公布日期 2016.01.06
申请号 JP20140207258 申请日期 2014.10.08
申请人 株式会社半導体エネルギー研究所 发明人 小山 潤
分类号 G11C19/28;G09G3/20;G09G3/36;G11C19/00;H01L29/786 主分类号 G11C19/28
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