发明名称 メモリ制御装置
摘要 <p>A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.</p>
申请公布号 JP5840451(B2) 申请公布日期 2016.01.06
申请号 JP20110228952 申请日期 2011.10.18
申请人 ルネサスエレクトロニクス株式会社 发明人 二ノ宮 康之
分类号 G06F13/28;G06F12/02 主分类号 G06F13/28
代理机构 代理人
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