| 摘要 |
A data processing apparatus 2 includes a first execution mechanism 4, such as an out-of-order processing circuitry, and a second execution mechanism 6 such as an in-order processing circuitry. Switching control circuitry 24 controls switching between which of the first execution circuitry and the second execution circuitry is active at a given time. Latency indicating signals indicative of the latency associated with a candidate switching operation to be performed are supplied to the switching control circuitry and used to control the switching operation. The latency indicating signals may be indicative of pending write operations to the registers of the first execution means. The control of the switching operation may be to accelerate the switching operation, prevent the switching operation, or perform early architectural state data transfer. The execution circuitries may differ. For example, one may be a high performance processor core, and the other a low power processor core. |
