发明名称 Method of manufacturing a semiconductor device
摘要 Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.
申请公布号 US9230948(B2) 申请公布日期 2016.01.05
申请号 US201414577859 申请日期 2014.12.19
申请人 Renesas Electronics Corporation 发明人 Osugi Eiji
分类号 H01L23/48;H01L25/00;H01L27/08;H01L23/00;H01L21/56;H01L21/78;H01L23/495;H01L25/07 主分类号 H01L23/48
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) providing on a mother substrate made of a metal first, second, third, fourth, and fifth electrodes, the first electrode provided in a first region, the second electrode provided in the first region and apart from the first electrode and arranged in a first direction, the fourth electrode provided in a second region and apart from the first electrode and arranged in a second direction orthogonal to the first direction, the third electrode provided in the second region and apart from the fourth electrode and arranged in the first direction in the second region, and the fifth electrode provided in a third region and apart from each of the first, second, third, and fourth electrodes, the third region being between the first region and second region; (b) placing a first semiconductor chip bonded onto an upper surface of the first electrode via a first conductive resin, placing a second semiconductor chip bonded onto an upper surface of the second electrode via a second conductive resin, placing a third semiconductor chip bonded onto an upper surface of the third electrode via a third conductive resin, and placing a fourth semiconductor chip bonded onto an upper surface of the fourth electrode via a fourth conductive resin; (c) after step (b), electrically coupling a first bonding pad of the first semiconductor chip to an upper surface of the fifth electrode via a first conductive member, electrically coupling a second bonding pad of the second semiconductor chip to the upper surface of the first electrode via a second conductive member, electrically coupling a third bonding pad of the third semiconductor chip to the upper surface of the fourth electrode via a third conductive member, electrically coupling a fourth bonding pad of the fourth semiconductor chip to the upper surface of the fifth electrode via a fourth conductive member, and electrically coupling the upper surface of the second electrode to the upper surface of the third electrode; (d) after step (c), forming a resin molding by sealing, with a resin, the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the first conductive member, the second conductive member, the third conductive member, the fourth conductive member, a portion of the first electrode, a portion of the second electrode, a portion of the third electrode, a portion of the fourth electrode, a portion of the fifth electrode, and an upper surface of the mother substrate; and (e) after step (d), peeling the mother substrate from the resin molding and exposing a lower surface of the first electrode, a lower surface of the second electrode, a lower surface of the third electrode, a lower surface of the fourth electrode, and a lower surface of the fifth electrode.
地址 Tokyo JP