Non-LUT field-programmable gate arrays

摘要

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

主权项

1. A logic block implemented in an integrated circuit, comprising:
a plurality of cells formed in said integrated circuit, each of said cells consisting of data inputs, one or more select inputs, one of a logic gate and the functional equivalent of the logic gate, and one or more programmably selectable inverters coupled to said logic gate, each of said data inputs to said cell consisting only of an input to at least one of said logic gate and one of said one or more programmably selectable inverters, said logic gate including a logic gate output coupled to one of an output of said cell and one of said one or more programmably selectable inverters, said one or more select inputs configured for enabling or disabling each of said one or more programmably selectable inverters; a tree structure arrangement comprising a number of levels formed by said cells; a plurality of inputs to said tree structure in a first level of said tree structure comprising said data inputs to said cells in said first level; and an output from said tree structure in a last level of said tree structure.