发明名称 |
Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die |
摘要 |
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. |
申请公布号 |
US9230609(B2) |
申请公布日期 |
2016.01.05 |
申请号 |
US201313908973 |
申请日期 |
2013.06.03 |
申请人 |
Rambus Inc. |
发明人 |
Frans Yohan |
分类号 |
G11C5/02;G11C5/06;H01L25/065 |
主分类号 |
G11C5/02 |
代理机构 |
Peninsula Patent Group |
代理人 |
Kreisman Lance;Peninsula Patent Group |
主权项 |
1. A packaged semiconductor memory device, comprising:
a data pin; a first memory die comprising:
a first data interface coupled to the data pin, anda first memory core having a plurality of banks; and a second memory die stacked with the first memory die and comprising a second memory core having a plurality of banks; wherein: a respective bank of the first memory core and a respective bank of the second memory core are to perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal; and the first data interface is to provide aggregated data from the parallel column access operations to the data pin. |
地址 |
Sunnyvale CA US |