Multi-phase clock generator

摘要

Embodiments provide a multi-phase clock generator. The clock generator includes a loop oscillator, a RC filter, a bias current source and a frequency injection source. The loop oscillator includes N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1. The N levels of CMOS phase inverters have the same structures, each of which includes a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source. As an effect of RC filter, a clock input signal inputted by the frequency injection source is applied to the first level tail current source, while other tail current sources are not influenced. Injection locking is induced, such that phase noise and frequency stray can be reduced.

主权项

1. A multi-phase clock generator, comprising:
a loop oscillator, a RC filter, a bias current source and a frequency injection source; wherein the loop oscillator comprises N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1; wherein the N levels of CMOS phase inverters have the same structures, each of which comprises a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source; wherein an input end of the ith level CMOS phase inverter is connected to an output end of the (i−1)th level CMOS phase inverter, an output end of the ith level CMOS phase inverter is connected to an input end of the (i+1)th level CMOS phase inverter, and an input end of the first level CMOS phase inverter is connected to an output end of the Nth level CMOS phase inverter, i represents an integral number greater than 1 and less than N; wherein the RC filter comprises a first capacitor and a first resistor; wherein the frequency injection source is adapted for inputting a clock input signal which is then injected through the first capacitor to the tail current source of the first level CMOS phase inverter; wherein the clock input signal is isolated, by the RC filter, from the bias current source and the tail current sources of the CMOS phase inverters from the second level to the Nth level of the loop oscillator; wherein the loop oscillator outputs a clock output signal whose frequency is the same as a frequency of the clock input signal inputted by the frequency injection source under the effect of injection locking.