| 摘要 |
A memory interface for a plurality of DRAM devices comprising an input DRAM address matching module includes a local memory comprising a plurality of data entries, wherein the plurality of data entries comprising a plurality of DRAM addresses and a plurality of associated pointers, and wherein the plurality of associated pointers comprise output DRAM addresses, and a matching mechanism coupled to the local memory, wherein the matching mechanism is configured to receive the input DRAM address, wherein the matching mechanism is configured to determine whether the input DRAM address is specified in the plurality of data entries, and when the input DRAM address is specified in the plurality of data entries, the matching mechanism is configured to output an associated pointer associated with the input DRAM address. |
| 主权项 |
1. A memory interface for a plurality of DRAM devices comprising an input DRAM address matching module comprising:
a local memory comprising a plurality of data entries, wherein the plurality of data entries comprising a plurality of DRAM addresses and a plurality of associated pointers, and wherein the plurality of associated pointers comprise output DRAM addresses; and a matching mechanism coupled to the local memory, wherein the matching mechanism is configured to receive the input DRAM address, wherein the matching mechanism is configured to determine whether the input DRAM address is specified in the plurality of data entries, and when the input DRAM address is specified in the plurality of data entries, the matching mechanism is configured to output an associated pointer associated with the input DRAM address, wherein the matching mechanism further comprises, a first portion configured to receive the plurality of data entries from the local memory, wherein the plurality of data entries are logically ordered within a binary search tree comprising N layers, wherein each node of the binary search tree is associated with a data entry from the plurality of data entries, wherein nodes in an upper M layers of the binary search tree are associated with a first subset of the plurality of data entries, and wherein nodes in lower N-M layers of the binary search tree are associated with a second subset of the plurality of data entries, and a second portion coupled to the first portion, wherein the second portion is configured to receive the input DRAM address, and wherein the second portion is configured to perform comparisons of the input DRAM address to the first subset of the plurality of data entries in parallel, wherein the second portion comprises a plurality of comparators; wherein N>M, wherein M is selected based upon a number of the comparators, and wherein the second subset of the plurality of data entries are logically ordered within a truncated binary search tree comprising N-M layers. |
