Embedded control channel for high speed serial interconnect

摘要

Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.

主权项

1. A method comprising:
embedding a control channel in a serial interconnect having a plurality of data lanes, wherein operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis having a nominal periodicity and implementing a link state cycle employed for transmitting control information and non-control information over the interconnect, the link state cycle including a first period comprising a link control period during which link control information may be transmitted over the one or more lanes, the first period having a starting time that is implemented at a nominal periodicity.