IMPROVED FORMATION OF SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES

摘要

Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

主权项

1. A semiconductor device comprising:
a substrate having a n-type field effect transistor (nFET) and a p-type FET (pFET); an n-type source and drain (S/D) region in the nFET; a first silicide feature directly on the n-type S/D region; a p-type S/D region in the pFET; and a second silicide feature directly on the p-type S/D region.