发明名称 |
SEGMENTED DIGITAL-TO-TIME CONVERTER CALIBRATION |
摘要 |
This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information. |
申请公布号 |
US2015381337(A1) |
申请公布日期 |
2015.12.31 |
申请号 |
US201414318799 |
申请日期 |
2014.06.30 |
申请人 |
Intel Corporation |
发明人 |
Madoglio Paolo;Palaskas Georgios;Pellerano Stefano;Ravi Ashoke;Chandrashekar Kailash |
分类号 |
H04L7/00;H04B17/21 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
1. A calibration circuit for a segmented digital-to-time converter (DTC), the segmented DTC configured to receive reference frequency information and to provide processed frequency information, the calibration circuit comprising:
a calibration path configured to represent a segment of the segmented DTC; a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment; a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the segmented DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the segmented DTC using the timing error information. |
地址 |
Santa Clara CA US |