| 发明名称 |
EVADING FLOATING INTERRUPTION WHILE IN THE TRANSACTIONAL-EXECUTION MODE |
| 摘要 |
A computer implemented method and system for evading a floating interruption while a processor is in a transactional-execution (TX) mode. A floating interruption request can be detected, by a floating interrupt control mechanism, for a plurality of processors for execution by any one of the plurality of processors. An evasive action can be initiated for at least one of the plurality of processors in a transactional-execution mode, for evading the floating interruption such that another one of the plurality of processors can execute the floating interruption. |
| 申请公布号 |
US2015378945(A1) |
申请公布日期 |
2015.12.31 |
| 申请号 |
US201514845331 |
申请日期 |
2015.09.04 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Bradbury Jonathan D.;Busaba Fadi Y.;Cain, III Harold W.;Greiner Dan F.;Gschwind Michael Karl;Salapura Valentina;Schwarz Eric M. |
| 分类号 |
G06F13/26 |
主分类号 |
G06F13/26 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A computer implemented method for evading a floating interruption while a processor is in a transactional-execution (TX) mode, comprising:
detecting, by a floating interruption control mechanism, a floating interruption request for a plurality of processors for execution by any one of the plurality of processors; and initiating an evasive action for at least one of the plurality of processors in a transactional-execution mode for evading the floating interruption such that another one of the plurality of processors executes the floating interruption. |
| 地址 |
Armonk NY US |
