| 摘要 |
Provided is a memory device including an array of bit cells and a plurality of wordlines. Each bit cell of the array of the bit cells is selectively coupled to one of the wordlines. Access to a selected bit cell of the array of bit cells needs an assert voltage on a selected wordline associated with the selected bit cell. A reading assist circuit is provided to reduce the assert voltage of the selected wordline when reading access to the selected bit cell is performed. The reading assist circuit makes the selected word line selectively come in contact with an additional wordline of the wordlines, thereby reducing the assert voltage. |
