| 摘要 |
A method for modifying a fault-tolerant processing system (FTS) including a pair of partner sets of two processors (PA1/PA2; PB1/PB2) operating in microsynchronization at a first or low processing frequency (FL) and connected to a respective system bus (BA; BB) operating at a bus clock frequency (FB) lower than the first processing frequency (FL). The method consists in: selecting the system bus (BA) associated to one of the sets of "slow" processors (PA1/PA2); replacing the other set of "slow" processors (PB1/PB2) by a set of "fast" processors (PB1'/PB2'); synchronizing the operation of the remaining "slow" set with that of the "fast" set by: executing by each set (PA1/PA2; PB1'/PB2') one processor cycle during a first cycle (T1) of the bus clock frequency (FB) and generating a synchronization signal (SA1; SB1) at the end of this first bus clock cycle; executing during each following bus clock cycle (T2-T6) an additional processor cycle and generating a synchronization signal (SA1; SB1) until one of the sets, i.e. the slowest, fails to generate the latter synchronization signal. In case of upgrading of the system, similar steps are executed for replacing the remaining slow set (PA1/PA2) by another set of fast processors (PA1'/PA2').
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