CODEC TO REDUCE SIMULTANEOUSLY SWITCHING OUTPUTS

摘要

Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

主权项

1. An apparatus, comprising:
a row decode circuit configured to decode a first portion of a given data word of a first plurality of data words, wherein each data word of the first plurality of data words includes N data bits, and wherein N is a positive integer greater than one; a column decode circuit configured to decode a second portion of the given data word of the first plurality of data words, wherein the second portion is not the same as the first portion; a memory array coupled to the row decode circuit and the column decode circuit, wherein the memory array is configured to:
store a second plurality of data words, wherein each data word of the second plurality of data words includes M data bits, and wherein M is a positive integer greater than N; andretrieve a given data word of the second data words dependent upon the decoded first portion of the given data word and the decoded second portion of the given data word.