INTEGRATED CIRCUIT HAVING MAIN ROUTE AND DETOUR ROUTE FOR SIGNAL TRANSMISSION AND INTEGRATED CIRCUIT PACKAGE INCLUDING THE SAME

摘要

The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured to receive a signal transmitted from the second via, a first detour circuit configured to receive a signal transmitted through the second buffer, a second detour circuit configured to receive a signal transmitted through the first buffer, a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit. Each of the first and second buffers and the first and second detour circuits transmits a signal in only one direction.

主权项

1. An integrated circuit comprising:
first and second vias, each of the first and second vias being configured to penetrate a plurality of chips and configured to provide a signal transmission route between the plurality of chips; a first buffer connected between an output terminal of the first via and a detour node, and configured to receive a signal transmitted from the first via; a second buffer connected between an output terminal of the second via and the detour node, and configured to receive a signal transmitted from the second via; a first detour circuit configured to receive a signal transmitted through the second buffer; a second detour circuit configured to receive a signal transmitted through the first buffer; a first selector configured to selectively output one of the signal transmitted from the first via and a signal transmitted through the first detour circuit, based on a state of signal transmission through the first via; and a second selector configured to selectively output one of the signal transmitted from the second via and a signal transmitted through the second detour circuit, based on a state of signal transmission through the second via, wherein each of the first and second buffers and the first and second detour circuits is configured to transmit a signal in only one direction.