发明名称 FIXED CYCLE SIGNAL MONITORING CIRCUIT AND BACKUP SIGNAL GENERATION CIRCUIT FOR CONTROLLING LOAD
摘要 PROBLEM TO BE SOLVED: To quickly detect anomaly when a control circuit that includes a microcomputer fails.SOLUTION: A fixed cycle signal monitoring circuit includes; a signal input terminal 21a for inputting a watch dog signal SGw/d; a positive edge detection section 23 that detects rising edge timing of the SGw/d pulses; a negative edge detection section 24 that detects falling edge timing of the SGw/d pulses; and a timer section 25 that measures a period of time without detection of a positive or negative edge on the basis of output from the positive edge detection section and negative edge detection section, and generates a predefined anomaly detection signal when the measured time period exceeds a threshold. Thus, time required for clearing the timer section 25 on each edge is significantly reduced, enabling quick detection of anomaly thereby.
申请公布号 JP2015232766(A) 申请公布日期 2015.12.24
申请号 JP20140118840 申请日期 2014.06.09
申请人 YAZAKI CORP 发明人 WATARU KAZUHISA
分类号 G06F11/30;F02D41/22;F02D45/00 主分类号 G06F11/30
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