发明名称 SKIP INSTRUCTION TO SKIP A NUMBER OF INSTRUCTIONS ON A PREDICATE
摘要 A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.
申请公布号 US2015370561(A1) 申请公布日期 2015.12.24
申请号 US201414311222 申请日期 2014.06.20
申请人 Netronome Systems, Inc. 发明人 Stark Gavin J.
分类号 G06F9/30;G06F9/38 主分类号 G06F9/30
代理机构 代理人
主权项 1. A processor coupled to a memory system, the processor comprising: a fetch stage that causes a sequence of instructions to be fetched from the memory system, wherein the sequence of instructions includes a first instruction and a second instruction; a decode stage that first decodes the first instruction and then decodes the second instruction, wherein the decode stage can decode skip instructions; a register file read stage coupled to the decode stage, wherein the register file read stage includes a plurality of flag bits; and an execute stage that can carry out an instruction operation of an instruction, wherein the second instruction defines an instruction operation to be performed when the second instruction is executed by the processor, wherein if the first instruction is a skip instruction and if a predicate condition is satisfied then the instruction operation of the second instruction is not carried out by the execute stage even though the second instruction was decoded by the decode stage, wherein the predicate condition is specified by a predicate field of the skip instruction, and wherein the predicate condition is a specified function of values of at least one of the plurality of flag bits.
地址 Santa Clara CA US
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