FORMING GATE AND SOURCE/DRAIN CONTACT OPENINGS BY PERFORMING A COMMON ETCH PATTERNING PROCESS

摘要

One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

主权项

1. A method of forming conductive structures for a transistor device formed above an active region of a semiconducting substrate surrounded by an isolation region, the method comprising:
forming a gate structure that is positioned above said active region and said isolation region; forming a gate cap layer above said gate structure, said gate cap layer having a substantially uniform full thickness above the entire gate structure; performing at least one first recess etching process on a first portion of said gate cap layer positioned above said isolation region while masking a second portion of said gate cap layer positioned above said active region so as to thereby define a gate cap layer comprised of a reduced-thickness portion positioned above said isolation region and a full thickness portion positioned above said active region; forming a gate contact opening that extends through said reduced-thickness portion of said gate cap layer and exposes said gate structure; and forming a gate contact in said gate contact opening.