VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY

摘要

A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

主权项

1. A method for fabricating a vertical III-V nanowire field-effect transistor, the method comprising:
depositing a first layer of doped III-V semiconductor material on a substrate of III-V semiconductor material; depositing a layer of undoped III-V semiconductor material on top of said first layer of doped III-V semiconductor material; depositing a second layer of doped III-V semiconductor material on top of said layer of undoped III-V semiconductor material; growing a first dielectric layer on top of said second layer of doped III-V semiconductor material; depositing self-assembled monolayers of nanospheres on said first dielectric layer; and forming nanopillars using said nanospheres as a mask and said first dielectric layer as a hard mask to etch said second layer of doped III-V semiconductor material and said layer of undoped III-V semiconductor material using nanosphere lithography.