发明名称 |
IMAGER, IMAGING CIRCUIT, AND IMAGE PROCESSING CIRCUIT |
摘要 |
The number of channels is changed depending on an operation mode in an imager. An imaging control unit (240) determines the number of operation channels (W) according to the operation mode. A sensor section (210) outputs the imaging signal corresponding to each pixel according to the number of operation channels (W). A data transmission section (220) makes the serial conversion of the imaging signal to transfer it to an image processing unit (300) by a high-speed interface (signal line (229)) such as an LVDS according to the number of operation channels (W). A data receiving section (311) makes the parallel conversion of the transferred serial signal of each of the channels M bit-by-M bit. A data restoring section (500) detects the simulation code embedded into the parallel signal, extracts a data window, restores an imaging signal of a bit-length (n) from the data window, and supplies it to a signal line (319). A clock gating circuit (330) supplies a clock (CLK3) to a signal line (337) only while an effective flag (signal line (316)) shows to be effective.
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申请公布号 |
KR20100014213(A) |
申请公布日期 |
2010.02.10 |
申请号 |
KR20097000376 |
申请日期 |
2008.02.19 |
申请人 |
SONY CORPORATION |
发明人 |
KINOSHITA MASAYA;KAMEYA TAKASHI |
分类号 |
H04N5/335;H04N5/225;H04N5/343;H04N5/378 |
主分类号 |
H04N5/335 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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