发明名称 |
High Performance Pseudo Dynamic 36 Bit Compare |
摘要 |
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.
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申请公布号 |
US2009063774(A1) |
申请公布日期 |
2009.03.05 |
申请号 |
US20070850050 |
申请日期 |
2007.09.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHAN YUEN H.;CHEN ANN H.;LO KENNETH M.;WANG SHIE-EI |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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