| 摘要 |
<p>A transistor comprising a source region, a gate (10), a drain region (13), a gate dielectric layer (11, 12) for isolating the gate from an underlying body (14, 6), and a well region (5) at least partially extending under the gate to create a channel region, wherein the gate dielectric layer comprises a thinner portion (12) and a thicker portion (11), and wherein the thickness of the thicker portion is no more than 200nm.</p> |
