发明名称 TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS
摘要 <p>Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer (130) over a target layer (120); providing a second hard mask layer (140) over the first hard mask layer (130); providing a photoresist layer (150) over the second hard mask layer (140); forming a pattern in the photoresist layer (150); transferring the pattern into the second hard mask layer (140); and trimming the second hard mask layer (140) with the photoresist layer (150) on top of the second hard mask layer (140). The top surface of the second hard mask layer (140) is protected by the photoresist (150) and the target layer (120) is protected by the overlying first hard mask layer (130) during the trim etch, which can therefore be aggressive. ® KIPO & WIPO 2009</p>
申请公布号 KR20080112281(A) 申请公布日期 2008.12.24
申请号 KR20087024655 申请日期 2008.10.08
申请人 MICRON TECHNOLOGY, INC. 发明人 ABATCHEV MIRZAFER K.;SUBRAMANIAN KRUPAKAR MURALI;ZHOU BAOSUO
分类号 H01L21/027 主分类号 H01L21/027
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