CLOCKED PARAPHASE LOGICAL ELEMENT

摘要

FIELD: physics; computer engineering. ^ SUBSTANCE: invention relates to computer engineering and can be used in metal-insulator-semiconductor (MIS) integrated circuits when designing logic and arithmetic devices. The device has first and second CMIS inverters which are connected between a power bus and a clocked bus. The output of the first CMIS inverter is connected to the input of the second CMIS inverter and is the true output of the device. The output of the second CMIS inverter is connected to the input of the first CMIS inverter and is the complementary output of the device. The logical element has direct and inverse key circuits made from n-type transistors whose gates are connected to potential paraphase logic inputs of the device. First leads of the direct and inverse key circuits are connected to inputs of the second and first CMIS inverters respectively. Second leads of the direct and inverse key circuits are connected to corresponding current paraphase logic inputs of the device. ^ EFFECT: simplification of the device. ^ 1 dwg