发明名称
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a data transfer system for suppressing deterioration in data transfer efficiency caused by link adjustment. <P>SOLUTION: When a value of a timer counter 52 becomes "0", a link adjustment detection circuit 54 detects "0" of the timer counter 52 and sets "1" in a flag register 55 during link adjustment. Namely, the link adjustment detection circuit 54 instructs link adjustment. A link disconnection determination circuit 62 generates a signal for adjusting a timer set value handled by a timer set value selection circuit 50 in accordance with the number of errors that have occurred and outputs the signal to the timer set value selection circuit 50. Subsequently, the timer set value selection circuit 50 selects a timer set value indicated by the signal outputted by the link disconnection determination circuit 62. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP4463097(B2) 申请公布日期 2010.05.12
申请号 JP20040373618 申请日期 2004.12.24
申请人 发明人
分类号 G06F15/177 主分类号 G06F15/177
代理机构 代理人
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